Night depository line security

ABSTRACT

A line security system for use in intruder alarms for bank night depositories and the like. A termination unit at the secured premise responds to randomly spaced interrogation signals sent over lines from a central unit to generate return signals synchronized to the random signals. The termination unit includes an oscillator driven counter which sequentially emits pulses coded by the plugboard. An inhibit circuit stops the oscillator at the end of each response signal cycle. The termination of the interrogation pulse resets the counter to insure that it remains synchronized with a decoder at the central unit, and also disables the inhibit circuit so that the next interrogation pulse may restart the oscillator. The termination unit is powered by energy derived from the interrogation pulses and stored in a capacitor. The central unit sounds an alarm when no response signal occurs or after receipt of several successive response signals of improper or unsynchronized code.

United States Patent 1191 Edwards Apr. 2, 1974 NIGHT DEPOSITORY LINESECURITY Primary Examiner-Harold I. Pitts [75] Inventor: Richard C.Edwards, Brookfield, Attorney Agent or Flrmflwood Herron & Evans Conn.

57 ABSTRACT [73] Assignee: The Mosler Safe Company,

Hamilton, Ohio A line security system for use in intruder alarms forbank night depositories and the like. A termination [22] Ffled: July1972 unit at the secured premise responds to randomly [211 App, Neg273,839 spaced interrogation signals sent over lines from a central unitto generate return signals synchronized to the random signals. Thetermination unit' includes an [52] US. Cl. 340/151 R, 340/168 Xoscillator driven counter which sequentially emits [51] Int. Cl G08c l5,H04q 9/00 pulses coded by the plugboard. An inhibit circuit stops [58]Fleld of Search 340/408 409 151 R the oscillator at the end of eachresponse signal cycle. The termination of the interrogation pulse resetsthe [56] v References C'ted counter to insure that it remainssynchronized with a UNITED TATES PATENT decoder at the central unit, andalso disables the in- 3,313,160 4/1967 Goldman 340 151 x hibit Circuit80 that the next interrogation Putse y 3,383,658 5/1968 Martin 340/151 Xrestart the oscillator. The termination unit is powered 3,508,260 I5/1970 Stein 340/408 X by energy derived from the interrogation pulsesand 3,566,399 2/1971 Welt? v 340/409 R stored in a capacitor. Thecentral unit sounds an alarm 16] 10/1971 Ganlchotm 340/408 R when noresponse signal occurs or after receipt of sev- 3,706,086 12/1972Farnsworth 340/l5l X era. successive response signals of p p or ychronized code.

17 Claims, 2 Drawing Figures T TSQTIO RANDOMLY SPACED W6 $5 5.INTERROGATION PULSE GENERATOR RANDOM Homwfl d z 211i, PERIOD OFTERMINATION k 43sec FREE I UNIT OSCILLATOR ilifiig iiiiil if }LINES TOTERMINATION UNIT VIBRATOR l 4%? /flj SIGNAL /i/ /E K T e5, 6 9 w PQi'EIE gR 1 EQQQL 4 E k; l?

//7 n n n n A gig/mt 2 DIFF. DIFF. 5%, 5% 5; GENERATOR //j RESET 4 j 55A 4 4 1+2 9+2 l igz BE TIMER I 4t2 [TNT INTEGRATOR T T t-; R p n /42 I I69 10 1 o 1 7mm f/J9 air PATENTEI] APR 2 I974 SHEEI 2 0F 2 NIGHTDEPOSITORY LINE SECURITY The present invention relates to intrusionalarm line security systems, and more particularly, to a system whereina premise unit located at a protected area, such as at a bank nightdepository, transmits coded response signals to a central unit inresponse to random interrogation signals on the connecting lines.

Intruder alarm systems are in common use for protecting premises againstunauthorized intrusions. These systems normally employ some sort ofalarm condition sensor which responds to an abnormal condition at theprotected area. Commonly, these alarm sensors transmit a signalindicating this alarm condition over lines which connect the sensor atthe premise area with the central alarm unit. It is important in suchsystems that, for additional security, measures be taken to detect anytampering which may occur with the connecting lines. In the simpleralarm systems, the alarm condition may be indicated by a switchconnected in the lines which will be opened or closed upon the openingof a door or window or the like. Attempts are sometimes made byintruders to short circuit the lines across the switch or cut the linesto defeat the alarm. In somewhat more sophisticated devices, animpedance or signal generator is connected across the lines so that asimple opening or shortening of the leads can'be detected at the centralunit through a change in the'impedance or removal of the return signal.Devices employing signal generators may include transmitterswhich'operate independently or continuously to generate signals or mayinclude devices which respond when interrogated from the central unit.

The impedance termination systems can be defeated by substituting thecorrect impedance on the lines. With the signal generator type ofsystems, it-is sometimes encountered that an intruder might attempt tobreach the security of the system by recording the return signals on thelines and then retransmitting the recorded signal on the lines and backto the central unit so that he might thereafter proceed to break thelines to the alarm sensor. The likelihood of attempts such as this beingsuccessful can be substantially reduced by employing a randominterrogation system. With such systems, it is much more difficult forthe intruder to synthesize a proper return signal on the lines. Thesystem of this type, however, does require a degree of synchronizationbetween the interrogation signal and the return signal which respondsto'it so that lack of synchronization can be used to distinguish thesynthesized signal from a proper response.

It is a primary objective of the present invention to provide such asystem in which the premise unit is small, simple, and extremelycompact, and which derives its power primarily from the lines connectingit with the central unit.

The present invention is predicated in part upon the concept ofproviding a line security system having a premise unit which generates aresponse signal synchronized to randomly spaced interrogation pulses,and which premise unit includes a transmitter which employs a counterwhich generates a series of signals in response to an interrogationpulse and which counter is automatically reset by theinterrogation pulseso that the return in interrogation signals are maintained insynchronism.

The specific embodiment of the present invention disclosed belowprovides a premise unit employing an oscillator driven counter or shiftregister. The shift register has ten outputs which are energizedsequentially as the oscillator generates clock pulses to the register.The outputs of the shift register are selectively connectable through apatch panel to a transmitter output so that a binary code is generatedin accordance with the setting of the patch panel. In the specific codeemployed, two consecutive connections designate a onebit and a singleconnection designates a zero-bit, open connections providing the spacersbetween the bits.

The oscillator is normally held in an OFF condition and the shiftregister is held in a RESET condition both through a reset circuitconnected across the lines which is responsive to the absence of aninterrogation pulse on the lines. The occurrance of an interrogationsignal on the lines will remove the shift register reset signal andallow the oscillator to begin generating clock pulses to theshiftregister. After the clock starts, a flipflop is set which enables aclock inhibit circuit to automatically stop the clock when the shiftregister has completed its scan. Upon termination of the interrogationpulse, the shift register is'automatically reset and the inhibit circuitis disabled so that the clock can be restarted when the nextinterrogation pulse occurs on the lines.

The central unit is provided with a randomly spaced constant pulse widthinterrogation pulse generator and a receiver both connected to thelines. The receiver actuates an alarm when either of two conditionsoccurs. The first and most common condition is that of total absence ofa response signal to an interrogation pulse on the lines. This conditionwill immediately sound the alarm. The second condition is the presenceof areturn signal on the lines but in a formwhich does not correspond tothe proper code or which is not properly synchronized with theinterrogation signal. When this condition occurs, an alarm triggercircuit begins to integrate a signal which will sound an alarm ifseveral such occurances occur in sequence. This detects line tamperingbut will ignore a certain amount of error in the return signal as aresult of noise on the lines or in the system.

The termination unit is powered entirely by power derived from theinterrogation pulse. This energy is stored in a capacitor, thus,providing a compact premise unit.

Additionally, the termination unit may be provided with means whichallow recycling of the shift register and code selecting means, such asa flip-flop, and another plugboard so that other information such as atermination unit identification code may be added.

The advantages of the system reside in the ability to i provide the linesecurity system employing a random interrogation pulse responsivepremise unit which is highly compact, simple, and effective in detectinga breach of security on the system lines. The system is capable ofmicropower circuit construction.

These and other objectives and advantages of the present invention willbe more readily apparent from the following detailed description of thedrawings illustrating one preferred form of an alarm system embodyingprincipals of the present invention.

FIG. 1 is a logic and schematic diagram of a termination unit of a linesecurity system according to the present invention;

FIG. 2 is a schematic and logic diagram of a central unit of a linesecurity system according to the present invention.

The termination unit of FIG. 1 is normally employed in a burglar alarmsystem. This termination unit is located at a premise to be protected.The termination unit 10 is connected through a pair of lines 11 and 12to a central unit 100 (FIG. 2). The central unit will enunciate an alarmcondition at the premises protected by the termination unit. A typicalalarm condition results from the breaking of a closure as, for example,the unauthorized opening of a door. This condition is normally detectedby a switch connected in series with the lines 11 and 12. The switchopens upon the breaking of the closure to cause a condition which wouldbe detected by the central unit to enunciate the alarm condition.

The termination unit 10 is powered by electrical energy transmitted overthe lines 11 and 12 from the central unit. The unit 10 responds tointerrogation pulses on the lines 11 and 12 to return over the lines 11and 12 a signal representative of a secure condition. If the lines arebroken, the absence of the return signal will be detected by the centralunit and, thus, an alarm condition will be indicated.

The termination unit 10 has no power supply of its own, but instead itrelies entirely upon energy supplied over the lines 11 and 12 of thecentral unit. In this interrogation type system, in a normal state,there is no power transmitted over the lines 11 and 12. Instead, all ofthe energy to power the termination unit 10 is de rived from theinterrogation pulse. This pulse takes the form of a voltage on line 11which is positive with respect to the line 12 which is grounded. Theenergy from the central unit passes through a diode 14 from line 11 tocharge a storage capacitor 15.The capacitor 15 will be charged to theinterrogation pulse voltage which may be typically 12 volts. Theinterrogation pulse,

upon its occurrence on the lines 11 and 12, actuates a signal generatorwhich generates a secure condition signal on lines 21. This signal iscommunicated to a transmitter or modulator circuit 23 in the form of aseries of negative pulses which are impressed by way of the line 25 onthe line 11 upstream of the diode 14. The diode l4 prevents a dischargeof the capacitor 15 by the superimposition of the negative signal pulsesfrom line 25. The signal from line 25 represents coded information whichis identical to a reference code stored at the central unit. This signalis decoded by the central unit and compared with the reference signal todetect the presence or absence of a secure condition on the lines 11 and12. If the lines 11 or 12 are broken, the interrogation pulse will notcause the return of any signal and this condition when detected by thecentral unit will indicate the alarm state.

To reduce the likelihood of the success of more sophisticated attemptsto violate the line security, the interrogation pulses from the centralunit are randomly spaced. This makes it more difficult for an intruderto synthesize the interrogation pulse response and to feed it back alongthe lines 1] and 12 when the circuit is broken. This might be attempted,for example, by recording the pulse response and transmitting it back tothe central unit. Random interrogation makes it more difficult toproperly time the response. Such a system, however, must be able tosynchronize the return signal with a reference signal in the decoder.The present invention does this by synchronizing both with theinterrogation pulse. It provides a counter in the premise or terminationunit which is started and reset by the interrogation pulse. This isprovided by circuitry described below.

The signal generator 20 of the termination unit 10 includes anoscillator 31 which generates clock pulses 32 along line 33 to the clockinput 34 of the shift register 35. The shift register 35 is a circularshift register having 10 stages. The outputs of nine of these stages areconnected through blocking diodes 38 to a plugboard 39. As the shiftregister is clocked, output signals appear successively on the outputlines 37. The plugboard 39 allows the selective connection of each ofthe outputs 37 of the shift register 35 to the input 41 of the modulatorcircuit 23. The outputs 37 of the shift register 35, which are energizedin sequence, are each representative of a specific time in the signalcycle. The connections made by the plugboard 39 result in the impositionof a low-voltage signal during the time controlled by the respectiveposition of the shift register 35 on output line 21. Theplugboard-connection shown in FIG. 1 will result in a signal having theform of signal 43. The coding selected in the present circuit is suchthat a negative-going pulse of only one time period in width willrepresent a zero while a pulse having a two time period width willrepresent a one, thus giving a binary coded serial data transmission.The coded signal represented as 43 in the drawing will thus have theform of a digital number l0-l-0. This code is determined by the settingof the patch panel 39 connecting outputs 37 representing signals of oneclock pulse width beginning at times T,, T T T T and T to line 21 to themodulator 23. Time periods beginning at times T T and T denote spaceintervals.

The signal generator synchronizing circuit includes an interrogationpulse-responsive start and reset circuit 52, an oscillator startingcircuit 53 and an oscillator stopping or inhibiting circuit 54. Thecircuit 53 serves as an oscillator starting circuit by disabling theinhibiting circuit 54.

The circuit 52 includes a transistor 55 connected between the lines 11and 12 downstream of the diode 14. The base of the transistor 55 isconnected through a resistor/diode network from the line 11 upstream ofdiode 14. The collector of the transistor 55 is connected to a resetline 56 connected to the reset input 57 of the shift register 35. In theintervals between interrogation pulses, the transistor 55 isnonconductive and the signal on reset line 56 is positive, by virtue ofthe charge on the capacitor 15. This positive signal on line 56 holdsthe shift register 35 in reset condition during this interval betweeninterrogation pulses. The reset condition of the register 35 is onewherein the bit positions 1 through 9 of the shift register containszeros and the bit position 10 contains a one.

Line 56 is also connected to the input 61 of the oscillator 31 todisable the oscillator during the interval be tween interrogationpulses. This bit position 10 of the shift register 35 has its outputconnected to an input of an inverter 63 of the circuit 54. The OFF stateof the inverter 63 denotes the oscillator inhibit signal. This inhibitsignal is disabled, during this interval by the ONE- state output fromline 66 of the circuit 53. The circuit 53 includes a pair of NOR-gates67 and 68 connected in an R-S flip-flop circuit arrangement. Thisflip-flop is illustrated in an ON condition. It has a set input 71connected to the ninth position of the shift register 35 and a resetinput 72 connected to the reset line 56.

In its initial stand-by position, the termination unit will have a zerosignal appearing at the input lines 11 and 12. A position reset signalwill be present on line 56 holding the shift register in its resetcondition. The shift register 35 will thus have a ONE in the tenthposition and a zero in its other nine positions. Theoscillator will beinhibited only by the negative signal from the reset line 56 at itsinput 61. The flip-flop of the inhibit disable circuit 53 will be setgiving a positive signal on line 66, while the flip-flop 63 of inhibitcircuit 54 will be reset to zero.

At the beginning of the interrogation pulse, at time T the signal online 11 will go positive causing the transistor of circuit 52 toconduct, thus removing the reset signal from'line 56. This will cause azero signal to appear at the input 61 of the oscillator 31 which allowsthe oscillator to start generating sequential output pulses to the clockinput 34 of the shift register 35. This will cause the bit to betransferred from the tenth position to the first position of the shiftregister 35 as the first pulse is emitted from the oscillator at time TAs each subsequent pulse is emitted from the oscillator 31 along line33, the bit will progress through the shift register successivelycausing it to transmit output signals along the line 21 whenever therespective outputs 37 from the respective position of the shift register35 is connected by patch panel 39 thereto. As the bit progresses throughthe shift registerv 35 toward bit position 10, it is necessary to atsome time reset the flip-flop of the inhibit disable circuit 53 so as topermit the bit from position 10 to pass through the NOR-gate 64 to stopor inhibit the oscillator 31. This is provided by the output of bitposition 9 which is connected to the set input 71 of the flip-flopcircuit'53. When the bit enters this ninth position, the flip-flop 53 isset causing its output to assume a zero state enabling the inhibitcircuit 54. Thus, when the bit enters position '10 of the register 35,it is v transmitted along the output line 75 to the reset input of theinverter 63, causing the inverter to turn on, thus causing the output ofthe NOR-gate 64 to go positive inhibiting the oscillator 31. At sometime thereafter the interrogation pulse will cease at time T and thepositive signal on line 56 will reset the flip-flop of circuit 53 sothat the presence of the bit in the tenth position of the shift register35 will not prevent the restarting of the oscillator 31. The positivepulse on line 56 also holds the shift register in a reset condition sothat in the event that the shift register has erroneously stopped insome other than the reset condition, due perhaps to the incidence ofnoise, the register will be assured of being synchronized to its resetcondition for the beginning of the next interrogation cycle. Thepositive pulse or signal on line 56 also'holds the oscillator 31in adisabled condition.

Referring now to FIG. 2, the central unit is illustrated. This unitincludes a randomly spaced but constant width interrogation pulsegenerator 101 which includes a sawtooth generator 102 and a free-runningmulti-vibrator 103. The multi-vibrator is set to switch ON for 40milliseconds and OFF for a time which may be 40 milliseconds or less.The variable pulse spacing is achieved by the saw-tooth generator 102which is connected to the multi-vibrator 103 in such a manner that itsoutput affects the initial charge condition on the capacitor whichdetermines the OFF time of the multivibrator. Thus, a quasi-randomspacing between the positive pulses is achieved. The output of thesaw-tooth generator 102 is of low frequency having a period ofapproximately three seconds. Thus, the intervals between interrogationpulses will progressively decrease for a period of three seconds andthen abruptly increase toward a maximum of approximately 40milliseconds.

The general wave form of the interrogation pulses is represented by acurve 105 in FIG. 2. The output of the multi-vibrator 103 is connectedto the line 11 while the line 12 is connected to ground. These lines 11and 12 connect to the termination unit 10. The returned signal on thelines 11 and 12 is superimposed on the interrogation pulse and isrepresented by the curve 106 in FIG. 6. I

An alarm circuit illustrated generally at 110 comprises the rest of thecircuit shown in FIG. 2. This circuit includes an input 111 which isconnected from the line 11 to a signal at detector 112. The signalabsence detector 112 includes a differentiator and detector circuit 114and an intergrator 115. The input 111 from the line 11 is connected tothe input-of the integrator 115. The output of the integrator isconnected through an OR-gate 117 to an alarm signal generator 120. Aninterrogation signal, if allowed to accumulate in the integrator 115,will cause the alarm signal generator 120 to actuate. The signal absencedetector 112 has a second input 121 connected also to the line 11. Thisinput is transmitted through a differentiator and detector circuit 114which extracts from the pulse signal 105 the received information 106 onthe line 11. If this information is present in any form, whether in theproper code or not, a signal is emitted from the output 122 of thedifferentiator 114 to a reset input of the integrator 115 to reset theintegrator, thus preventing the occurence of the alarm signalindicationfln the case that a pulse passes with the totalabsence of anyreturn signal, such as will occur if the line is broken, the integratorl 15 will not be reset and the alarm condition will be indicated.

If'information is present upon the line 111, but is not in the propercoded form, this condition will be detected by the decoder circuit 125in combination with the comparator circuit 126. This decoder circuit 125has an input 128 also connected from the line 11. The decoder circuit125 includes a differentiator 131 having its input connected from thedecoder input 128. This differentiator responds to the trailing edges ofthe wave form 106. If the proper signal is present, pulses will beemitted at the output 132 of the differentiator 131 at times T T T and TThese pulses are transmitted to a one-shot multi-vibrator 134 whichoperates as a time delay for a period T which is equal to approximatelyltimes the normal spacing between the clock pulse outputs from theoscillator 31 in the termination unit 12 (FIG. 1). Thus, the output fromthe one shot multi-vibrator 134 will coincide with a negative pulse ofthe signal 106 only when that pulse is at least two time incrementslong. A pulse of a single time increment in length will not coincidewith the delayed signal from the output of the one-shot multi-vibrator134..

Thus, this information provides a means for distinguishing between thelonger pulses indicating a ONE-bit and the shorter pulses indicating aZERObit. The delayed pulses at the outputs of the multi-vibrator 134occur at times T T T and T These pulses are shaped to a proper width Aby being fed through a second one-shot multi-vibrator 138. The outputsof the multi-vibrator 138 are transmitted along line 139 to the clock,153 of a shift register 152. The data input of the register 152 isconnected from the output of an inverter amplifier 141 which has itsinput 142 also connected to line 11. The register 152 operates to AND,thus, the delayed pulses on line 139 and the signal 106 from thetermination unit distinguish between 1 and 0 code. For example, anoutput signal will only occur from the AND-gate 140 at time T and T Thissignal is transmitted to a data input 151 of the four-position shiftregister The clock input 153 of the shift register 152 enters from theline 139 so that each of the delayed pulses will clock the shiftregister 152. Thus, at time T a shift register will be clocked but azero bit will enter the shift register 152. Similarly, a one will entera time T and a zero at time T Thus, the shift register will attain afinal data content of 1-0-1-0. The outputs of the bit positions from theshift register 152 are each communicated to a respective one of a set offour two-input Exclusive-OR gates 16]. The other input of theseExclusive-OR gates is connected to a signal standard source 162. Thissource 162 consists of a plug-board 163 which selectably connects theinputs of the respective Exclusive-OR gates 161 to either positive ornegative signal sources thus establishing a reference signal. When anexact coincidence exists between the content of the shift register 152and the reference signal provided by the plugboard 163, a zero willappear at the output of the Exclusive-OR gates 165 which has its outputsof the Exclusive-OR gates 161. This condition is tested at the end ofthe interrogation pulse by a NOR-gate 166 which has one input connectedto the output of OR-gate 165 and the other input connected along line.167 to the line 11. Thus, the output of the OR-gate 165 is interrogatedonly at time T at the end of the interrogation pulse. Only ifcoincidence does occur will a positive signal appear at the output ofthe NOR-gate 166 and be transmitted to a reset input 171 of anintegrator 172. The integrator 172 has its output 173 connected to theinput of the OR-gate 117 to trigger the alarm generator 120. Theintegrator 172 has its input 175 connected to a positive signal source.Thus, the integrator 172 will continue to constantly integrate at a slowrate and, if not reset, eventually provide an alarm signal along line173 to trigger the alarm generator 120. A coincidence, therefore, asdetected by the NOR-gate 166, will reset the integrator through input171 and prevent it from ultimately obtaining an alarm condition. Thetime constant of the integrator 172 is such that it will take severalnoncomparison occurrences to allow an alarm to be triggered. This willprevent the indication of an alarm condition due to erroneousinformation caused by noise on the transmission lines.

The device described above operates very effectively to monitor thesecurity of a line between a central alarm unit and a remote locationsuch as a door to a closure. The termination unit of the systemdescribed above does not require a power source but derives all itspower from the lines 11 and 12. The termination unit can be manufacturedin an extremely compact form of at most a few cubic inches withconventional solid-state components. The double reset circuitry in thetermination unit, particularly the reset circuitry 54 which operatesupon completion of the generation of the responding signal and inaddition the reset circuitry 52 which insures that the register is resetat the beginning of every pulse serves to effectively synchronize theresponse to the interrogation pulse with the decoder in the central orpanel unit. This effectively provides a means for employing randomlyspaced interrogation pulses, thus enhancing the security of the lines inan extremely simple and compact security unit.

What is claimed is:

1. A line security premise unit having a line connectable to a centralstation, said unit being capable of transmitting on said line, inresponse to interrogation signals on said line, coded response signals,said premise unit comprising:

a counter;

a transmitter for generating a coded pulse signal on said line inresponse to the stepping of said counter;

said counter being started in response to the occurrence of each saidinterrogation signal on said line; and

said counter being'reset in response to the termination of each saidinterrogation signal;

whereby said coded pulse signals are maintained in synchronism with saidinterrogation signals.

2. The premise unit of claim 1 further comprising:

an oscillator for generating a periodic series of pulses to trigger saidcounter, said oscillator starting in response to the occurrence of eachinterrogation signal on said line.

3. The premise unit of claim 1 further comprising:

a plugboard coder connected between the output of said counter and saidline for establishing the code of said pulse signals on said line.

4. The premise unit of claim 1 further comprising:

a counter inhibit circuit responsive to a predetermined state of saidcounter for stopping the generation of coded information.

5. The premise unit of claim 4 further comprising:

an inhibit disabling circuit being set in response to the termination ofsaid interrogation pulse and being reset after the start of said counterbut before said counter reaches said predetermined state.

6. The premise unit of claim 1 further comprising:

a power storage element connected to said line;

said counter and transmitter being powered by energy from said storageelement;

said storage unit being charged by energy from said central station.

7. A line security premise unit having a line connectable to a centralstation, said unit being capable of transmitting on said line, inresponse to and in synchronism with random interrogation signals on saidline, coded response signals, said premise unit comprising:

a counter; a transmitter for generating a coded pulse signal on saidline in response to the stepping of said counter;

an oscillator for generating a periodic series of pulses to trigger saidcounter, said oscillator starting in response to the occurence of eachinterrogation signal on said line;

a counter inhibit circuit responsive to a predetermined state of saidcounter for stopping the generation of coded information;

an inhibit disabling circuit being set in response to the termination ofsaid interrogation pulse and being reset after the start of said counterbut before said counter reaches said predetermined state; and

a counter reset responsive to the termination of each said interrogationsignal on said line.

8. The premise unit of claim 7 further comprising:

means for selectively connecting the outputs of said counter to saidtransmitter to establish the code of said pulse signals on said line.

9. A synchronized random interrogation line security system comprising:

a central unit;

a premise unit located remote from said central unit:

a line electrically interconnecting said central unit and said premiseunit; said central unit comprising:

a. a signal generator for generating randomly spaced interrogationsignals, said generator having an output connected to said line,

b. an alarm signal generator,

c. a receiver having an input connected to said line,

said receiver being operative to decode pulse signals on said line;

d. a reference signal source,

e. means timed by said interrogation signal for comparing said decodedsignal and said reference signal, and g f. means for actuating saidalarm signal generator in accordance with the results of saidcomparison; and

said premise unit comprising:

a counter;

a transmitter for generating a coded pulse signal on said line inresponse to the stepping of said counter;

said counter being started in response to the occurrence of each saidinterrogation signal on said line; and

said counter being reset in response to the termination of each saidinterrogation signal;.

whereby said coded pulse signals are maintained in synchronisrn withsaid interrogation signals.

10. The system of claim 9 wherein said premise unit further comprises: I

an oscillator for generating a periodic series of pulses to trigger saidcounter, said oscillator starting in response to the occurrence of eachinterrogation signal on said line.

11. The system of claim 10 wherein said premise unit further comprises:

a plugboard coder connected between the output of said counter and saidline for establishing the code of said pulse signals on said line.

12. The system of claim 9 wherein said premise unit further comprises:

a counter inhibit circuit responsive to a predetermined state of saidcounter for stopping the generation of coded information.

13. The system of claim 9 wherein said premise'unit further comprises:

an inhibit disabling circuit being set in response to the termination.of said interrogation pulse and being reset after the start of saidcounter but before said counter reaches said predetermined state.

14. The system of claim 9 wherein said premise unit further comprises:

a power storage element connected to said line;

said counter and transmitter being powered by energy from said storageelement;

said storage unit being charged by energy from said central station.

15. The system of claim 9 wherein said receiver further comprises aregister for storing said decoded pulse signal; and

said comparing means are timed by the termination of said interrogationpulse. 16. The system of claim 9 wherein said central unit furthercomprises:

means responsive to the absence of information on said line foractuating said alarm signal generator.

said reference signal. 7

1. A line security premise unit having a line connectable to a centralstation, said unit being capable of transmitting on said line, inresponse to interrogation signals on said line, coded response signals,said premise unit comprising: a counter; a transmitter for generating acoded pulse signal on said liNe in response to the stepping of saidcounter; said counter being started in response to the occurrence ofeach said interrogation signal on said line; and said counter beingreset in response to the termination of each said interrogation signal;whereby said coded pulse signals are maintained in synchronism with saidinterrogation signals.
 2. The premise unit of claim 1 furthercomprising: an oscillator for generating a periodic series of pulses totrigger said counter, said oscillator starting in response to theoccurrence of each interrogation signal on said line.
 3. The premiseunit of claim 1 further comprising: a plugboard coder connected betweenthe output of said counter and said line for establishing the code ofsaid pulse signals on said line.
 4. The premise unit of claim 1 furthercomprising: a counter inhibit circuit responsive to a predeterminedstate of said counter for stopping the generation of coded information.5. The premise unit of claim 4 further comprising: an inhibit disablingcircuit being set in response to the termination of said interrogationpulse and being reset after the start of said counter but before saidcounter reaches said predetermined state.
 6. The premise unit of claim 1further comprising: a power storage element connected to said line; saidcounter and transmitter being powered by energy from said storageelement; said storage unit being charged by energy from said centralstation.
 7. A line security premise unit having a line connectable to acentral station, said unit being capable of transmitting on said line,in response to and in synchronism with random interrogation signals onsaid line, coded response signals, said premise unit comprising: acounter; a transmitter for generating a coded pulse signal on said linein response to the stepping of said counter; an oscillator forgenerating a periodic series of pulses to trigger said counter, saidoscillator starting in response to the occurence of each interrogationsignal on said line; a counter inhibit circuit responsive to apredetermined state of said counter for stopping the generation of codedinformation; an inhibit disabling circuit being set in response to thetermination of said interrogation pulse and being reset after the startof said counter but before said counter reaches said predeterminedstate; and a counter reset responsive to the termination of each saidinterrogation signal on said line.
 8. The premise unit of claim 7further comprising: means for selectively connecting the outputs of saidcounter to said transmitter to establish the code of said pulse signalson said line.
 9. A synchronized random interrogation line securitysystem comprising: a central unit; a premise unit located remote fromsaid central unit; a line electrically interconnecting said central unitand said premise unit; said central unit comprising: a. a signalgenerator for generating randomly spaced interrogation signals, saidgenerator having an output connected to said line, b. an alarm signalgenerator, c. a receiver having an input connected to said line, saidreceiver being operative to decode pulse signals on said line; d. areference signal source, e. means timed by said interrogation signal forcomparing said decoded signal and said reference signal, and f. meansfor actuating said alarm signal generator in accordance with the resultsof said comparison; and said premise unit comprising: a counter; atransmitter for generating a coded pulse signal on said line in responseto the stepping of said counter; said counter being started in responseto the occurrence of each said interrogation signal on said line; andsaid counter being reset in response to the termination of each saidinterrogation signal; whereby said coded pulse signals are maintained insynchronism with said interrogation signAls.
 10. The system of claim 9wherein said premise unit further comprises: an oscillator forgenerating a periodic series of pulses to trigger said counter, saidoscillator starting in response to the occurrence of each interrogationsignal on said line.
 11. The system of claim 10 wherein said premiseunit further comprises: a plugboard coder connected between the outputof said counter and said line for establishing the code of said pulsesignals on said line.
 12. The system of claim 9 wherein said premiseunit further comprises: a counter inhibit circuit responsive to apredetermined state of said counter for stopping the generation of codedinformation.
 13. The system of claim 9 wherein said premise unit furthercomprises: an inhibit disabling circuit being set in response to thetermination of said interrogation pulse and being reset after the startof said counter but before said counter reaches said predeterminedstate.
 14. The system of claim 9 wherein said premise unit furthercomprises: a power storage element connected to said line; said counterand transmitter being powered by energy from said storage element; saidstorage unit being charged by energy from said central station.
 15. Thesystem of claim 9 wherein said receiver further comprises a register forstoring said decoded pulse signal; and said comparing means are timed bythe termination of said interrogation pulse.
 16. The system of claim 9wherein said central unit further comprises: means responsive to theabsence of information on said line for actuating said alarm signalgenerator.
 17. The system of claim 9 wherein said central unit furthercomprises: an integrator having a signal input independent of said codedsignal and an output connected to said alarm signal generator foractuating said alarm when said integrator output reaches a predeterminedvalue; and the output of said comparison means being connected to saidintegrator so as to reset said interrogation upon coincidence of saiddecoded signal and said reference signal.